1. Field of the Invention
The present invention relates to a trench isolation structure, a semiconductor device having this structure, and a trench isolation method, and more particularly, to a trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top corners of a trench and increasing the oxidation amount at these areas.
2. Description of the Related Art
Isolation between elements of a semiconductor device can be usually achieved by local oxidation of silicon (LOCOS) or trench isolation.
Between the two, the LOCOS method is simply conducted, and can simultaneously form wide isolation films and narrow isolation films. However, in the LOCOS method, a bird beak  is formed by side oxidation, and thus an isolation region becomes wide, which leads to a reduction in the effective area of a source/drain region. Also, in the LOCOS method, stress which depends on the difference in a thermal expansion coefficient is concentrated at the edges of an oxide film during formation of a field oxide film, which causes crystal defects to be formed on a silicon substrate and results in a large amount of leakage current.
Hence, a trench isolation technique is necessarily required. Using a trench isolation technique, an isolation region can be kept small compared to the above-described LOCOS technique, with an effective isolation length made long at the same isolation width by forming a trench in a silicon substrate and filling the trench with a dielectric material such as oxide.
Among several processes for achieving isolation using trenches, how to form the profile of a trench is very important to produce a stable device. That is, a trench depth, a trench angle and the shape of a trench edge must be appropriately controlled. In particular, when shallow trench isolation (STI) is used in highly-integrated semiconductor devices, it is not too much to say that the electrical characteristics of devices are determined by the profile of the edge portions of a trench.
FIG. 1 is a cross-sectional view for explaining a problem which has been encountered in a conventional STI method. Here, reference numeral 1 is a semiconductor substrate, reference numeral 3 is an isolation film embedded in an STI region, reference numeral 5 is a gate oxide film, and reference numeral 7 is a gate electrode.
As shown in FIG. 1, the following problems occur when the edge portions of a trench are formed with a sharp angle of almost 90xc2x0. First, a gate conductive layer covers the top corner portions of a trench during formation of a gate, so that an electric field is concentrated at the corners of a trench. As shown in FIG. 2, this leads to a hump phenomenon in which a transistor is turned on twice, and an inverse narrow width effect, resulting in degradation of the performance of transistors.
FIG. 3 is a graph showing an inverse narrow width effect occurring in an STI structure. As shown in this graph, an inverse narrow width effect represents a reduction in threshold voltage with a decrease in the channel width of a transistor. Here, reference character X represents data acquired before a hump phenomenon occurs, and reference character Y represents data acquired after a hump phenomenon occurs.
The second problem occurring when the edge portions of a trench are formed with a sharp angle of almost 90xc2x0 is degradation of the reliability of devices, such as, the dielectric breakdown of a gate oxide film caused by formation of a thin gate oxide film at the edge portions of a trench or by concentration of an electric field on the gate oxide film around the edges of a trench.
Several methods have been proposed to solve the above problems. One method is disclosed in U.S. Pat. Nos. 5,861,104 and 5,763,315.
U.S. Pat. No. 5,861,104 discloses a method of rounding the upper corners of a trench by improving a method of etching a trench. U.S. Pat. No. 5,763,315 discloses a method of rounding the upper edges of a trench by forming a (111) plane having a high oxidation rate on a semiconductor substrate with (100) crystal planes, using a wet etching technique or the like, and of preventing a degradation in the reliability of transistors and a gate oxide film by increasing the thickness of the gate oxide film which is formed on the upper edges of a trench.
The present invention intends to provide a structure for forming a (111) crystal plane on the upper edges of a trench to increase the thickness of a gate oxide film to be formed on these regions while rounding the upper edges of a trench, resulting in a significant improvement in the characteristics of transistors, and a fabrication method thereof.
An object of the present invention is to provide a trench isolation structure which can improve the reliability of transistors and a gate dielectric film by increasing the thickness of a gate oxide film at the upper edges of a trench while simultaneously rounding the upper edges of a trench.
Another object of the present invention is to provide a semiconductor device having an improved isolation structure, so that a hump phenomenon and an inverse narrow width effect are prevented.
Still another object of the present invention is to provide a trench isolation method by which the upper edges of a trench are rounded, and thus the thickness of a gate oxide film at the upper edges of a trench is increased.
The first object is achieved by a trench isolation structure including: a trench formed in non-active regions of a semiconductor substrate, the top edges of the trench being rounded; an inner wall oxide film formed on the inner wall of the trench; a liner formed on the surface of the inner wall oxide film, the top of the liner being recessed from the surface of the semiconductor substrate; and a dielectric film for filling the trench in which the inner wall oxide film and the liner have been formed.
It is preferable that the inner wall oxide film has a thickness of 10 to 150 xc3x85, and that the top ends of the liner are recessed by 0 to 500 xc3x85 from the surface of the semiconductor substrate, so that the upper edges of a trench are satisfactorily rounded.
The second object is achieved by a semiconductor device having a trench isolation structure, including: a trench formed in non-active regions of a semiconductor substrate, the top edges of the trench being rounded; an inner wall oxide film formed on the inner wall of the trench; a liner formed on the surface of the inner wall oxide film, the top of the liner being recessed from the surface of the semiconductor substrate; a dielectric film for filling the trench in which the inner wall oxide film and the liner have been formed; a gate dielectric film formed on active regions of the semiconductor substrate except for the trench, the edge portions of the gate dielectric film being thicker than the central portion; and a gate electrode formed on the gate dielectric film.
Preferably, the surface of the semiconductor substrate other than in the trench has a (100) plane, and the surface of a semiconductor substrate rounded at the top edges of the trench has a (111) plane.
The third object is achieved by a trench isolation method including: forming a trench in non-active regions of a semiconductor substrate; forming an inner wall oxide film on the inner wall of the trench; forming a silicon nitride liner on the surface of the inner wall oxide film; filling the trench with a dielectric film; and etching part of the silicon nitride liner so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.
The step of forming the trench includes: forming a pad oxide film on the semiconductor substrate; forming a pad nitride film on the pad oxide film; forming an etch mask pattern for defining regions on which the trenches are to be formed, using a photolithographic process; and forming the trenches by etching parts of the semiconductor substrate using the etch mask pattern. The step of filling the trench with a dielectric film includes: depositing a dielectric film on the resultant substrate on which the inner wall oxide film and the silicon nitride liner have been formed; and planarizing the surface of the dielectric film,
Planarization of the dielectric film is achieved by chemical mechanical polishing (CMP) or etchback using the pad nitride film as an etch stop layer. The step of removing a pad nitride film which remains on the active regions of the semiconductor substrate is further included after the step of planarizing the surface of the dielectric film.
The step of removing the pad nitride film is followed by the step of etching part of the silicon nitride liner so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate. The step of removing the pad nitride film is performed by wet etching.
After the step of etching the pad nitride film and part of the liner, the step of removing the pad oxide film is further included. The step of removing the pad oxide film can be followed by the step of oxidizing the surface of the semiconductor substrate.
According to the present invention, the amount of oxidation at the upper edges of a trench can be greatly increased in an oxidation process for forming a gate oxide film. This is accomplished by limiting the thickness of an inner wall oxide film formed on the inner wall of a trench to a certain level and forming a dent where the top portion of a liner is recessed from the surface of a semiconductor substrate. That is, the amount of oxidation at the upper edges of a trench in a semiconductor substrate is increased during subsequent oxidation for forming a gate oxide film, without rounding the upper edges of a trench on purpose, which results in rounding of the upper edges of a trench. The thickness of a gate oxide film at the upper edges of a trench is greater than at the center of an active region of a semiconductor substrate outside the trench. Thus, a hump phenomenon and an inverse narrow width effect occurring due to concentration of an electric field at the upper edges of a trench can be suppressed, and the reliability of a gate dielectric film can be improved.